Semiconductor memory devices, including flash memory, typically utilize memory cells to store data as an electrical value, such as an electrical charge or voltage. A flash memory cell, for example, includes a single transistor with a floating gate that is used to store a charge representative of a data value. Flash memory is a non-volatile data storage device that can be electrically erased and reprogrammed. More generally, non-volatile memory (e.g., flash memory, as well as other types of non-volatile memory implemented using any of a variety of technologies) retains stored information even when not powered, as opposed to volatile memory, which requires power to maintain the stored information. When non-volatile memory systems are implemented in storage networks, such as disaggregated storage networks, central processing unit (CPU) systems are situated between network connected hosts and non-volatile memory to facilitate storage. The CPU systems receive and buffer data in memory, such as DRAM memory, while the data is routed between the network host and the non-volatile memory storage for reading or writing data. The CPU systems and their associated buffers, however, have not been keeping up with the speeds of networks and non-volatile memory storage and have become a bottleneck.
One aspect of the performance bottleneck is computing parity for data written to data storage systems, such as solid state drive systems. If parity is generated in a host or in intermediate CPU systems situated between network connected hosts and non-volatile memory, the parity computation becomes a further bottleneck for high-performance writes. Therefore, it would be desirable to avoid having to perform parity computations on the host(s) or intermediate CPU systems situated between network connected hosts and non-volatile memory.